1. Field of the Invention
The present invention relates to a matrix-type display device and, more specifically, to a matrix-type display device with low power consumption.
2. Description of the Related Art
In active matrix display devices, the driver circuits generally employ shift registers or decoder circuits. This specification will describe the case of using decoder circuits.
FIG. 15 shows the configuration of an example of a conventional matrix-type display device. This matrix-type display device in FIG. 15 consists of a signal line counter 1501, a signal line decoder 1502, a signal line sampling circuit 1503, a scanning line counter 1504, a scanning line decoder 1505, and an m-row/n-column pixel matrix portion 1506.
To produce m or more different binary outputs, the signal line counter 1501 is composed of counter circuits of i stages (i satisfies 2i&gt;m) that operate in synchronism with a signal line clock signal 1507 (see FIG. 3)
To produce n or more different binary outputs, the scanning line counter 1504 is composed of counter circuits of j stages (j satisfies 2j&gt;n) that operates in synchronism with a scanning line clock signal 1508 (see FIG. 3).
The signal line decoder 1502 is a logic circuit that is so constructed as to select a particular signal line in response to an output of the signal line counter 1501.
The scanning line decoder 1505 is a logic circuit that is so constructed as to select a particular scanning line in response to an output of the scanning line counter 1504.
The signal line sampling circuit 1503 is a switching circuit that outputs, in synchronism with a pixel signal 1509, a display signal to pixels selected by an output of the signal line decoder 1502.
In the pixel matrix portion 1506, pixels (see FIG. 6) are arranged in matrix form on a plane. FIG. 6 shows a circuit configuration of each pixel. In FIG. 6, reference numerals 601 and 602 denote a scanning line and a signal line, respectively. Each pixel consists of a liquid crystal element 604, an auxiliary capacitor 605, and an n-channel thin-film transistor 603 whose gate receives an output of the scanning line decoder 1505 and source receives an output of the signal line sampling circuit 1503.
The operation of the conventional matrix-type display device will be described below.
First, a description will be made of an operation of displaying one line, that is, pixels connected to a single output line of the scanning line decoder 1505.
Attention is paid to the k-th line from the top in the vertical direction (hereinafter referred to simply as "k-th line"). When the output of the scanning line decoder 1505 for the k-th line turns a high potential (hereinafter abbreviated as "H"), the gate electrodes of all the k-th line pixels receive "H" and hence source-drain conduction is established in all the n-channel thin-film transistors of the k-th line.
During the course of the above operation, as the signal counter 1501 counts up in response to the signal line clock signal 1507, signal lines are sequentially selected from the left-side end of the k-th line by the signal line decoder 1502 and a video signal is sampled by the signal line sampling circuit 1503. Thus, display signals are sequentially written to the respective pixels, that is, a one-line writing operation is finished.
Next, a description will be made of an operation of displaying one frame.
As the scanning line counter 1504 counts up in synchronism with the scanning line clock signal 1508, scanning lines are sequentially selected from the top of one frame by the scanning line decoder 1505 and are given an output "H." The above-described one-line display is effected when the gate signal of each line is "H." One frame is displayed in this manner.
As described above, in the conventional matrix-type display device, as the number of signal lines of the signal line counter 1501 or the number of scanning lines of the scanning line counter 1504 increases, the number of flip-flop circuits in the counter circuits in which the holding signal varies in synchronism with each one-period clock decreases.
FIGS. 5A and 5B show the configuration of a flip-flop circuit. In FIGS. 5A and 5B, reference numeral 501 denotes a flip-flop circuit; 502, an inverted clock input line; 503, a clock input line; 504, a data input line; 505, an output line; and 506, an inverted output line.
In the above situation, the clock line capacitance, which is the clock line wiring capacitance plus the capacitance of elements that are connected to the clock lines, may cause a problem. The clock line capacitance is charged and discharged every time the clock signal to the counter circuits varies, and therefore consumes power even when there is no variation in the holding signal.
If it is prevented that a clock is input to circuit portions the inventors recognized that preventing the clock from being input to the circuit portions consumption due to the existence of the clock line capacitance could be reduced as much and hence the amount of heat generation could also be reduced.
Further, the elements are always supplied with a power supply voltage and leak current occurs therein. This is another factor of undue power consumption. If it is prevented that a power supply voltage is supplied to circuit portions where no variation occurs in the holding signal or the output signal, the power consumption due to leak current could be reduced as much and the amount of heat generation could also be reduced.